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31 August 2026

Semicon 2.0 Operational Framework Issued Across Six Pillars, Covering Design, Fabs, Packaging and Talent

The second phase of India’s semiconductor programme extends support across the value chain, including chip design, manufacturing equipment and materials, fabrication, packaging, research and workforce development. Applications will initially remain open for three years, while supported projects may run for up to six years

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Key Details

The Ministry of Electronics and Information Technology’s 31 August 2026 update on the Semicon 2.0 Scheme confirms that notifications have been issued for all six pillars, covering ten support categories.

  • Design: Strategic and commercial semiconductor intellectual property, chips and system-on-chips, along with a deployment-linked incentive

  • Machines and materials: Development of the wider semiconductor-manufacturing ecosystem

  • Fabrication: Silicon wafer fabs; compound semiconductor, photonics, sensor, MEMS and discrete-semiconductor fabs; and display fabs

  • Packaging: Assembly, Testing, Marking and Packaging and Outsourced Semiconductor Assembly and Test facilities

  • Research: Advanced semiconductor technologies

  • Talent: Expansion of the specialised engineering workforce

Operating framework: The scheme will initially accept applications for three years; projects will generally have up to six years for implementation; and a mid-term assessment is planned after three years.


Semicon 2.0 Moves Beyond Manufacturing Plants

The first phase of India’s semiconductor programme concentrated heavily on attracting fabrication and packaging investments. Semicon 2.0 retains these activities but adds more explicit support for the capabilities surrounding them.

The inclusion of semiconductor machinery, materials, intellectual property, advanced research and talent recognises that a fabrication plant alone does not create a complete semiconductor ecosystem. Competitiveness also depends on specialised chemicals, equipment, design tools, process knowledge, packaging and a qualified supplier base.

The scheme’s ten categories allow different parts of this ecosystem to be assessed separately. The release does not specify a total financial outlay or how fiscal support will be distributed among the pillars.


Design Support Now Extends to Deployment

The design pillar contains three categories:

  1. semiconductor intellectual property, chips, system-on-chips and modules for national or strategic priorities;

  2. intellectual property and chip design for the commercial market; and

  3. a Deployment-Linked Incentive for designs that enter use.

The third category is particularly significant. Design programmes can generate prototypes without achieving commercial production or adoption. Linking support to deployment could shift attention towards whether an Indian-designed chip is fabricated, integrated into a product and purchased by an end user.

The notification details will determine what qualifies as deployment, how domestic intellectual property is verified and whether incentives reward production volume, commercial sales or use in strategically important systems.


India Semiconductor Mission Will Control the Project Pipeline

The India Semiconductor Mission (ISM) will invite applications, conduct technical and financial appraisal, recommend applicants and oversee implementation. It may use the Centre for Development of Advanced Computing to support the design and deployment categories.

The Ministry of Electronics and Information Technology will provide budgetary support, while ISM will make disbursements according to the approved conditions. A mid-term review after three years may recommend changes or continuation.

This arrangement gives ISM responsibility across project selection and monitoring. Transparent appraisal criteria will be important because the six pillars involve very different capital requirements, technological risks and implementation periods.


The Talent Target Has Been Expanded

The government states that India trained 85,000 semiconductor engineers in four years, completing what had initially been set as a ten-year target. A further one lakh engineers are now proposed to be trained.

Students from Tier-II and Tier-III cities have reportedly designed more than 250 chips. The next challenge is to connect this design activity with fabrication access, verification tools, industry placements and commercial product development.

The Minister also projected that India could account for close to 10% of the global semiconductor market in coming years and that the emerging ecosystem could create 50,000–60,000 direct jobs. These are stated expectations, not outcomes already achieved.


What Are ATMP and OSAT Facilities?

Assembly, Testing, Marking and Packaging (ATMP) covers the later stages of semiconductor production in which fabricated wafers are cut into individual chips, packaged, tested and prepared for use.

An Outsourced Semiconductor Assembly and Test (OSAT) company provides these services to chip designers and manufacturers. These facilities generally require less capital than leading-edge fabrication plants but are critical to turning fabricated wafers into usable and reliable chips.


Policy Relevance

Semicon 2.0 creates a broader support framework; the policy challenge is now sequencing investments across an interdependent value chain.

  1. Fabs need suppliers: Manufacturing incentives will deliver deeper domestic value only if equipment, materials, maintenance and packaging capabilities develop alongside fabrication capacity.

  2. Design needs customers: Deployment-linked support should connect Indian chip designs with electronics, automotive, telecom, defence and other domestic buyers rather than stopping at prototype development.

  3. Training needs absorption: The additional one lakh engineers will strengthen the ecosystem only if curricula, fabrication exposure and industry demand produce relevant employment and research opportunities.

The three-year application window and mid-term assessment provide a point at which the government can compare approved investment with actual construction, technology transfer, domestic sourcing, chip deployment and employment. These outcomes will give a clearer measure of progress than the number of approvals alone.


Relevant Question for Policy Stakeholders: How will Semicon 2.0 allocate support among large fabrication projects and the less visible design, materials, equipment and research capabilities on which their competitiveness depends?


Follow the Full Update Here: Government Issues Notifications for All Six Pillars of Semicon 2.0

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